Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
SIGNAL FUNCTIONAL DESCRIPTION
Table 6. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
Notes
PCI Interface
5V tolerant
3.3V PCI
PCIAD0:31
PCI Address/Data bus. Multiplexed address and data bus
PCI bus command or Byte Enable
I/O
I/O
5V tolerant
3.3V PCI
PCIC3:0[BE3:0]
PCI Parity. Parity is even across PCIAD0:31 and
PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an
address or data phase. The PCI device that drove PCIAD0:31
is responsible for driving PCIParity on the next PCI bus clock.
5V tolerant
3.3V PCI
PCIParity
I/O
Driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
5V tolerant
3.3V PCI
PCIFrame
PCIIRDY
I/O
I/O
4
4
Driven by the current PCI bus master. Assertion of PCIIRDY
indicates that the PCI initiator is ready to transfer data.
5V tolerant
3.3V PCI
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is ready to
transfer data.
5V tolerant
3.3V PCI
PCITRDY
PCIStop
I/O
I/O
I/O
4
4
4
The target of the current PCI transaction can assert PCIStop
to indicate to the requesting PCI master that it wants to end
the current transaction.
5V tolerant
3.3V PCI
Driven by the target of the current PCI transaction. A PCI
target asserts PCIDevSel when it has decoded an address
and command encoding and claims the transaction.
5V tolerant
3.3V PCI
PCIDevSel
Used during configuration cycles to select the PCI slave
interface for configuration
5V tolerant
3.3V PCI
PCIIDSel
PCISErr
I
5
4
Used for reporting address parity errors or catastrophic
failures detected by a PCI target.
5V tolerant
3.3V PCI
I/O
Used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD0:31,
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the
data in which bad parity is detected.
5V tolerant
3.3V PCI
PCIPErr
I/O
4
5V tolerant
3.3V PCI
PCIClk
PCIReset
PCIINT
Used as the asynchronous PCI clock.
PCI specific reset
I
5V tolerant
3.3V PCI
O
O
PCI Interrupt. Open-drain output (two states; 0 or open
circuit).
5V tolerant
3.3V PCI
Req0 when internal arbiter is used, or Gnt when external
arbiter is used. IF PCI bus is used, pull this signal up;
otherwise, pull down.
5V tolerant
3.3V PCI
PCIReq0[Gnt]
I
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used
I
4
Gnt0 when internal arbiter is used, or Req when external
arbiter is used
5V tolerant
3.3V PCI
PCIGnt0[Req]
O
AMCC Proprietary
DS2011
43
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
