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NPE405H-3BA266CZ 参数 Datasheet PDF下载

NPE405H-3BA266CZ图片预览
型号: NPE405H-3BA266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP NPe405H嵌入式处理器 [PowerNP NPe405H Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 70 页 / 1343 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.01 – April 18, 2007  
NPe405H – PowerNP NPe405H Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 6 of 9)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.  
Signal Name  
Description  
I/O  
Type  
Notes  
DMA request. Used by peripheral slaves to request a data  
transfer. Following a system reset, the default mode of the  
signals is active-low. They may be programmed to active-high  
using the DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[DMAReq0:3]  
I
1
DMA acknowledge. Used to indicate to peripherals that data  
transfer is complete. Following a system reset, the default  
mode of the signals is active-low. They may be programmed  
to active-high using the DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[DMAAck0:3]  
O
End Of Transfer/Terminal Count. Indication by peripherals  
that all data has been transferred, or by DMA controller that  
programmed amount of data has been transferred. Following  
a system reset, the default mode of the signals is active-low.  
They may be programmed to active-high using the  
DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[EOT0:3/TC0:3]  
I/O  
1
48  
DS2011  
AMCC Proprietary  
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