欢迎访问ic37.com |
会员登录 免费注册
发布采购

NPE405H-3BA266CZ 参数 Datasheet PDF下载

NPE405H-3BA266CZ图片预览
型号: NPE405H-3BA266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP NPe405H嵌入式处理器 [PowerNP NPe405H Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 70 页 / 1343 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第45页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第46页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第47页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第48页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第50页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第51页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第52页浏览型号NPE405H-3BA266CZ的Datasheet PDF文件第53页  
Revision 1.01 – April 18, 2007  
NPe405H – PowerNP NPe405H Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 7 of 9)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.  
Signal Name  
Description  
I/O  
Type  
Notes  
External Master Peripheral Interface  
Peripheral Reset. Used by an external master and  
synchronous peripheral slaves.  
5V tolerant  
3.3V LVTTL  
ExtReset  
HoldReq  
HoldAck  
ExtReq  
ExtAck  
O
I
Hold Request. Used by an external master to request  
ownership of the peripheral bus.  
5V tolerant  
3.3V LVTTL  
1, 5  
6
Hold Acknowledge. Used by the NPe405H to transfer  
ownership of peripheral bus to an external master.  
5V tolerant  
3.3V LVTTL  
O
I
External Request. Used by an external master to indicate it is  
prepared to transfer data.  
5V tolerant  
3.3V LVTTL  
1
External Acknowledgement. Used by the NPe405H to  
indicate that a data transfer occurred.  
5V tolerant  
3.3V LVTTL  
O
I
6
Hold Primary. Used by an external master to indicate the  
priority of a given transfer (0 = high, 1 = low).  
5V tolerant  
3.3V LVTTL  
HoldPri  
1
Bus Request. Used when the NPe405H needs to regain  
control of peripheral interface from an external Master.  
5V tolerant  
3.3V LVTTL  
BusReq  
O
Internal Peripheral Interface  
Serial Clock used to provide an alternative clock to the  
internally generated serial clock. Used in cases where the  
allowable internally generated baud rates are not satisfactory.  
This input can be individually connected to either or both  
UART0 and UART1.  
5V tolerant  
3.3V LVTTL  
UARTSerClk  
I
1
1
5V tolerant  
3.3V LVTTL  
UART0_Rx  
UART0_Tx  
UART0 Receive data.  
I
O
I
5V tolerant  
3.3V LVTTL  
UART0 Transmit data.  
5V tolerant  
3.3V LVTTL  
[UART0_DCD]  
[UART0_DSR]  
[UART0_CTS]  
[UART0_DTR]  
[UART0_RTS]  
[UART0_RI]  
UART0 Data Carrier Detect.  
UART0 Data Set Ready.  
UART0 Clear To Send.  
UART0 Data Terminal Ready.  
UART0 Request To Send.  
UART0 Ring Indicator.  
1
1
1
5V tolerant  
3.3V LVTTL  
I
5V tolerant  
3.3V LVTTL  
I
5V tolerant  
3.3V LVTTL  
O
O
I
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL r  
1
AMCC Proprietary  
DS2011  
49  
 复制成功!