Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Bit
15:10
9
Description
Reserved. Hardwired to 0.
Fast Back-to-Back Enable. This bit enables fast back-to-back capability for bus master transaction. The S5320
is a target-only device and hardwires this bit to a 0.
8
System Error Enable. Setting this bit to a 1 allows the S5320 to drive the SERR# signal. Setting to a 0 will dis-
able the output driver. The assertion of RESET# will set this bit to a 0. The SERR# pin driven active normally
signifies a parity error occurred during a PCI address phase.
7
6
Wait Cycle Enable. Controls whether a device implements address/data stepping. This bit is hardwired to 0 as
the S5320 does not uses stepping.
Parity Error Enable. This bit allows the S5320 to drive the PERR# and to generate a SERR# signal. A one
allows the parity generation and a 0 will disable generation of a parity error indication. This bit is set to 0 when
RESET# is asserted.
5
4
Palette Snoop Enable. Enables VGA compatible devices to perform palette snooping. This bit is hardwired to a
0 as the S5320 is not a PCI-based VGA device.
Memory Write and Invalidate Enable. This bit enables bus masters to generate Memory Write and Invalidate
PCI bus commands when set to a 1. When set to 0, bus masters generate memory write commands instead.
The S5320 is a PCI target only and therefore hardwires this bit to 0.
3
2
1
Special Cycle Enable. Setting this bit to one enables devices monitoring of PCI special cycles. The S5320 does
not monitor (or generate) special cycles and hardwires this bit to 0.
Bus Master Enable. This bit allows a PCI device to function as a Bus Master. The S5320 is a PCI target device
only and hardwires his bit to 0.
Memory Space Enable. This bit enables S5320 memory region decodes to any of the five defined base address
register memory regions and the Expansion ROM Base Address Register. This bit is cleared to 0 when RESET#
is asserted.
0
I/O Space Enable. This bit enables S5320 I/O region decodes to any of the five defined base address register I/
O regions. This bit is cleared to 0 when RESET# is asserted.
32
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