Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Class Code Register (CLCD)
This 24-bit, read-only register is divided into three one-
byte fields: the base class byte at location 0Bh, the
sub-class byte at 0Ah, and the programming interface
byte at 09h. The default setting for the base class is
FFh, which indicates that the device does not fit into
the thirteen base classes defined in the PCI Bus Spec-
ification. It is possible, however, through use of the
external non-volatile memory to change the value of
this register. Refer to the PCI specification for details.
Class Code
Register Name:
Address Offset:
Power-up value:
Boot-load:
09h-0Bh
FF0000h
External nvRAM offset 049h-4Bh
Read Only
24 Bits
Attribute:
Size:
Figure 11. Class Code Register
@0Ah
@09h
@0Bh
7
7
0
07
0
Base Class
Sub-Class
Prog I/F
36
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
