Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
PCI Configuration Space Header
31
24 23
16 15
8 7
00
DEVICE ID
VENDOR ID
00
04
08
STATUS
COMMAND
REV ID
CACHE LINE SIZE
CLASS CODE
HEADER TYPE
BIST
LATENCY TIMER
0C
10
14
18
1C
20
BASE ADDRESS REGISTER #0
BASE ADDRESS REGISTER #1
BASE ADDRESS REGISTER #2
BASE ADDRESS REGISTER #3
BASE ADDRESS REGISTER #4
BASE ADDRESS REGISTER #5
24
28
2C
RESERVED = 0's
SUBSYSTEM ID
SUBSYSTEM VENDOR ID
EXPANSION ROM BASE ADDRESS
RESERVED = 0's
30
34
38
3C
RESERVED = 0's
MAX_LAT
MIN_GNT
INTERRUPT PIN
INTERRUPT LINE
LEGEND
EPROM IS DATA SOURCE (READ ONLY)
CONTROL FUNCTION
EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT)
EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT)
HARD-WIRED TO ZEROES
Note: Some registers are a combination of the above. See individual sections
for full description.
28
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
