Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Bit
Description
15
Detected Parity Error. This bit is set whenever the S5320 detects a parity error. It is set independent of the state
of Command Register Bit 6. The bit is cleared by writing a 1.
14
13
12
11
10:9
8
Signaled System Error. This bit is set whenever the S5320 generates the SERR# signal. This bit can be reset by
writing a 1.
Received Master Abort. Bus master devices set this bit to indicate a bus master transaction has been termi-
nated due to a master abort. The S5320 is a target device and hardwires this to 0.
Received Target Abort. This bit is set by a bus master when its transaction is terminated by a target abort from
the currently addressed target device. This bit is required for bus masters and is hardwired to 0 in the S5320.
Signaled Target Abort. This bit is set the target device whenever it terminates a transaction with a target abort.
The S5320 does not issue target aborts and hardwires this bit to 0.
Device Select Timing. These bits are read-only and define the DEVSEL# timing for a target device. The S5320
is a medium PCI device.
Data Parity Reported. Only implemented by bus mastering devices to notify a parity error has been detected.
This is not applicable to the S5320 and is hardwired to 0.
7
Fast Back-to-back Capable. This read-only bit indicates if a target device supports fast back-to-back transac-
tions. The S5320 supports this feature and hardwires the bit to 1.
6
UDF Supported. 1 = device supports user-definable features. 0 = device does not support user- definable fea-
tures. The S5320 implements definable memory regions and hardwires this bit to 0.
5
66 MHz Capable. 1 = device is capable of running at 66 MHz. 0 = device is capable of running at 33 MHz. This
bit is hardwired to 0.
4:0
Reserved. Hardwired to zero.
34
DS1656
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