Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
PCI Status Register (PCISTS)
This register contains PCI device status information.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Only
applicable bits are used by the S5320; those which are
not used are hardwired to 0. Status bits within this reg-
ister are designated as “write one clear,” meaning that
in order to clear a given bit, a 1 must be written. All R/
W/C bits written with a 0 are left unchanged. These
bits are identified in Figure 9 as (R/WC). Those which
are Read Only are shown as (RO).
PCI Status
Register Name:
Address Offset:
Power-up value:
Boot-load:
06h-07h
0200h
not used
Read Only Read/Write Clear
16 bits
Attribute:
Size:
Figure 9. PCI Status Register
15 14 13 12 11 10
9
1
8
0
7
1
6
0
54
0
0
X
X
0
0
0
0
Reserved = 00's
Reserved (RO)
66 Mhz Capable
UDF Supported
Fast Back-to-Back Capable
(RO)
Data Parity Reported (RO)
DEVSEL# Timing Status
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
Signaled Target Abort (R/WC)
Received Target Abort (RO)
Received Master Abort (RO)
Signaled System Error (R/WC)
Detected Parity Error (R/WC)
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
