Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
PCI Command Register (PCICMD)
This 16-bit register provides basic control over a
device’s ability to respond to or perform PCI accesses.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Four of
the ten implemented bits are required by the S5320;
those which are not required are hardwired to 0. The
definitions for all the fields are provided here for
completeness.
PCI Command
04h-05h
Register Name:
Address Offset:
Power-up value:
Boot-load:
0000h
not used
Read/Write (R/W on 4 bits, R/O for
all others)
Attribute:
Size:
16 bits
Figure 8. PCI Command Register
15
9
0
8
X
7
0
6
X
5
0
4
0
3
0
2
0
1
X
0
X
Reserved = 00
Fast Back-to-Back
SERR# Enable
Wait Cycle Enable
PERR# Enable
Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycle Enable
Bus Master Enable
Memory Access Enable
I/O Access Enable
AMCC Confidential and Proprietary
DS1656
31
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
