Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this con-
figuration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification. This
section describes each of the configuration space fields—its address, default values, initialization options, and bit
definitions—and also provides an explanation of its intended usage.
Table 10. Configuration Registers
Address Offset
00h–01h
02h–03h
04h–05h
06h–07h
8h0
Abbreviation
VID
Register Name
Vendor Identification Register
DID
Device Identification Register
Command Register
PCICMD
PCISTS
RID
Status Register
Revision Identification Register
Class Code Register
09h–0Bh
0Ch
CLCD
CALN
LAT
Cache Line Size Register
Latency Timer Register
Header Type Register
Built-in Self-test Register
Base Address Registers (0-5)1
Reserved
0Dh
0Eh
HDR
0Fh
BIST
10h–27h
28h–2Bh
2Ch–2Dh
2Eh–2Fh
30h–33h
34h–3Bh
3Ch
BADR0-BADR5
–
SVID
Subsystem Vendor Identification Register
Subsystem Identification Register
Expansion ROM Base Address Register
Reserved
SID
XROM
–
INTLN
INTPIN
MINGNT
MAXLAT
–
Interrupt Line Register
Interrupt Pin Register
3Dh
3Eh
Minimum Grant Register
Maximum Latency Register
Not used
3Fh
40h–FFh
1. BADR 5 is not implemented in the S5320.
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