16–6
Chapter 16: Understanding Timing in MAX II Devices
Calculating Timing Delays
Figure 16–3.
External Timing Parameter (t
PD2
TRI
MAX II
Device
Note to
(1)
t
PD2
= t
IN
+ t
DL
+ t
LUT
+ t
COMB
+ t
FASTIO
+ (t
OD
+
Δt
OD
)
LUT
Figure 16–4.
External Timing Parameter (t
CO
LE
Register
Notes to
(1)
t
CO
= t
GLOB
+ t
C
+ t
CO
+ (N x t
R4
/4 + M x t
C4
/4) + (t
IODC
or t
IODR
) + (t
OD
+
Δt
OD
)
(2) The constants N and M are subject to change according to the position of the LAB in the entire device.
Figure 16–5.
LE Register Clear and Preset Time (t
CLR
LE
Register
Note to
(1)
t
CLR
= t
GLOB
+ t
C
+ t
CLR
+ (N x t
R4
/4 + M x t
C4
/4) + (t
IODC
or t
IODR
) + (t
OD
+
Δt
OD
)
Figure 16–6.
LE Register Clear and Preset Time (t
PRE
LE
Register
Note to
(1)
t
PRE
= t
GLOB
+ t
LOCAL
+ t
C
+ t
PRE
+ (N x t
R4
/4 + M x t
C4
/4) + (t
IODC
or t
IODR
) + (t
OD
+
Δt
OD
)
Setup and Hold Time from an I/O Data and Clock Input
The Quartus II software might insert additional routing delays from the input pin to
the register input to ensure a zero hold time for the LE register. Altera recommends
that you use the Quartus II Timing Analyzer to obtain the setup time and hold time.
See
and
ALTERA [ ALTERA CORPORATION ]
