16–8
Chapter 16: Understanding Timing in MAX II Devices
Conclusion
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Distance between the signal source and destination
Various interconnect lengths where some interconnects are truncated at the edge
of the device
Conclusion
The MAX II device architecture has predictable internal timing delays that can be
estimated based on signal synthesis and placement. The Quartus II Timing Analyzer
provides the most accurate timing information. However, you can use the timing
model along with the timing parameters listed in the
chapter in the
MAX II Device Handbook
to estimate a design’s performance before
compilation. Both methods enable you to accurately predict your design’s in-system
timing performance.
Referenced Documents
This chapter references the following document:
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chapter in the
MAX II Device Handbook
Document Revision History
shows the revision history for this chapter.
Table 16–5.
Document Revision History
Date and Revision
October 2008,
version 2.1
December 2007,
version 2.0
Changes Made
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Summary of Changes
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—
Updated New Document Format.
Updated t
PD2
information in
Added t
COMB
information in
Updated
Updated
to
Updated
section.
Added
section.
Added document revision history.
Previously published as Chapter 17. No changes to content.
Added section Programmable Input Delay.
Updated Table 16–1. Various parameter naming updates.
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December 2006,
version 1.4
January 2005,
version 1.3
December 2004,
version 1.2
June 2004,
version 1.1
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