16–4
Chapter 16: Understanding Timing in MAX II Devices
Timing Models
Table 16–3.
Internal Timing Microparameters for MAX II UFM (Part 2 of 2)
Parameter
t
EB
t
BE
t
EPMX
t
RA
t
OE
t
OSCS
t
OSCH
Description
Maximum delay between
ERASE
rising edge to UFM
BUSY
signal rising edge.
Minimum delay allowed from UFM
BUSY
signal going low to
ERASE
signal going low.
Maximum length of
busy
pulse during an erase.
Maximum read access time. The delay incurred between the
DRSHFT
signal going low to the first bit of
data observed at the data register output.
Delay from
OSC_ENA
signal reaching UFM to rising clock of
OSC
leaving the UFM.
Maximum delay between the
OSC_ENA
rising edge to the
ERASE/PROGRAM
signal rising edge.
Minimum delay allowed from the
ERASE/PROGRAM
signal going low to the
OSC_ENA
signal going
low.
Timing Models
Timing models are simplified block diagrams that illustrate the delays through Altera
devices. Logic can be implemented on different paths. You can trace the actual paths
used in your design by examining the equations listed in the Quartus II Report File
(.rpt) for the project. You can then add up the appropriate internal timing parameters
to estimate the delays through the device.
The MAX II architecture has a globally routed clock. The MultiTrack interconnect
ensures predictable performance, accurate simulation, and accurate timing analysis
across all MAX II device densities and speed grades.
shows the timing model for MAX II devices. The timing model is the
preliminary version which is subject to change. The final version of the timing model
will be released once available.
Figure 16–1.
MAX II Device Timing Model
Output and Output Enable
Data Delay
t
R4
Data-In/LUT Chain
User
Flash
Memory
t
LOCAL
t
IODR
t
IOE
Logic Element
LUT Delay
t
C4
Output Routing
Delay
t
LUT
Register Control
Delay
t
COMB
t
CO
t
SU
t
H
t
PRE
t
CLR
t
FASTIO
I/O Input Delay
t
IN
Input Routing
Delay
t
DL
Output
Delay
t
OD
t
XZ
t
ZX
I/O Pin
t
C
I/O Pin
INPUT
t
GLOB
Global Input Delay
To Adjacent LE
Register Delays
From Adjacent LE
Combinational Path Delay
Data-Out
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