Chapter 16: Understanding Timing in MAX II Devices
Internal Timing Parameters for MAX II UFM
16–3
Table 16–2.
Internal Timing Microparameters (Part 2 of 2)
Parameter
t
IOE
t
DL
t
IODR
t
OD
Description
Internal generated output enable delay. The delay from an internally generated signal on the interconnect to
the output enable of the tri-state buffer.
Input routing delay. The delay incurred from the row I/O pin used as input to the LE adjacent to it.
Output data delay for the row interconnect. The delay incurred by signals routed from an interconnect to an
I/O cell.
Output delay buffer and pad delay. Refer to
Timing Model and Specifications
section in the
chapter in the
MAX II Device Handbook
for delay adders associated with different
I/O standards, drive strengths, and slew rates.
Output buffer disable delay. The delay required for high impedance to appear at the output pin after the
output buffer’s enable control is disabled. Refer to
Timing Model and Specifications
section in the
chapter in the
MAX II Device Handbook
for delay adders associated with different
I/O standards, drive strengths, and slew rates.
Output buffer enable delay required for the output signal to appear at the output pin after the tri-state
buffer's enable control is enabled. Refer to
Timing Model and Specifications
section in the
chapter in the
MAX II Device Handbook
for delay adders associated with different
I/O standards, drive strengths, and slew rates.
Delay for a column interconnect with average loading. The t
C4
covers a distance of four LAB rows.
Delay for a row interconnect with average loading. The t
R4
covers a distance of four LAB columns.
Local interconnect delay.
t
XZ
t
ZX
t
C4
t
R4
t
LOCAL
Internal Timing Parameters for MAX II UFM
Timing parameters for MAX II user flash memory (UFM) are the timing delays
contributed by the UFM architectural elements, which cannot be measured explicitly.
All timing parameters are shown in italic type.
defines the timing
microparameters for MAX II UFM.
Table 16–3.
Internal Timing Microparameters for MAX II UFM (Part 1 of 2)
Parameter
t
ASU
t
AH
t
ADS
t
ADH
t
DSS
t
DSH
t
DDS
t
DDH
t
DCO
t
DP
t
PB
t
BP
t
PPMX
t
AE
Description
Address register shift signal setup to address register clock.
Address register shift signal hold from address register clock.
Address register data in setup to address register clock.
Address register data in hold from address register clock.
Data register shift signal setup to data register clock.
Data register shift signal hold from data register clock.
Data register data in setup to data register clock.
Data register data in hold from data register clock.
Delay incurred from the data register clock to data register output when shifting the data out.
PROGRAM
signal to data clock hold time.
Maximum delay between
PROGRAM
rising edge to UFM
BUSY
signal rising edge.
Minimum delay allowed from UFM
BUSY
signal going low to
PROGRAM
signal going low.
Maximum length of busy pulse during a program.
Minimum
ERASE
signal to address clock hold time.
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