Chapter 16: Understanding Timing in MAX II Devices
Calculating Timing Delays
16–5
Calculating Timing Delays
You can calculate approximate pin-to-pin timing delays for MAX II devices with the
timing model shown in
and by referring to the
chapter in the
MAX II Device Handbook.
Each external timing parameter
is calculated from a combination of internal timing parameters.
through
show the external timing parameters for the MAX II device family. To
calculate the delay for a signal that follows a different path through the MAX II
device, refer to the timing model to determine which internal timing parameters to
add together.
For the most precise timing results, use the Quartus II Timing Analyzer, which
accounts for the effects of secondary factors such as placement and fan-out.
Figure 16–2.
External Timing Parameter (t
PD1
)
MAX II
Device
TRI
LUT
Note to
(1)
t
PD1
= t
IN
+ N x t
R4
/4 + M x t
C4
/4 + t
LUT
+ t
COMB
+ t
FASTIO
+ (t
OD
+
Δt
OD
)
lists the numbers of LABs according to device density.
Table 16–4.
Numbers of LABs According to Device Density
Device Density
EPM240
EPM570
EPM1270
EPM2210
N LAB Rows
4
7
10
13
M LAB Columns
6
12
16
20
Dt
OD
is the adder delay (see note to
for the t
OD
microparameter when
using an I/O standard other than 3.3-V LVTTL with 16 mA current strength.
f
Refer to the
chapter in the
MAX II Device Handbook
for
adder delay values.
The following is an example:
t
PD1
for the EPM240 device using an I/O standard of 3.3-V LVTTL fast slew rate with a
drive strength of 16 mA:
t
PD1
= t
IN
+ 4 × t
R4
/4 + 6 x t
C4
/4 + t
LUT
+ t
COMB
+ t
FASTIO
+ t
OD
……(a)
t
PD1
for the EPM240 device using an I/O standard of 2.5-V LVTTL fast slew rate with a
drive strength of 7 mA: t
PD1
= (a) + (Dt
OD
of 2.5-V LVTTL fast slew 7 mA)
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