16–2
Chapter 16: Understanding Timing in MAX II Devices
Internal Timing Parameters
Table 16–1.
External Timing Parameters
Parameter
t
PD1
Description
Pin-to-pin delay for the worst case I/O placement with full a diagonal path across the device with
combinational logic implemented in a single look-up table (LUT) in a logic array block (LAB) adjacent to
output pin. Fast I/O Connection is used from the adjacent logic element (LE) to the output pin.
Pin-to-pin delay for the best case I/O placement with combinational logic (2-input AND gate) implemented
in a single edge LE adjacent to the input pin. The longest pin path of the two inputs is shown. Fast I/O
Connection is used from the adjacent LE to the output pin.
Time to clear register delay. The time required for a low signal to appear at the external output, measured
from the input transition.
Global clock setup time. The time that data must be present at the input pin before the global
(synchronous) clock signal is asserted at the clock pin.
Global clock hold time. The time that data must be present at the input pin after the global clock signal is
asserted at the clock pin.
Global clock to output delay. The time required to obtain a valid output after the global clock is asserted at
the clock pin.
Minimum global clock period. The minimum period maintained by a globally clocked counter.
t
PD2
t
CLR
t
SU
t
H
t
CO
t
CNT
Internal Timing Parameters
Within a device, the timing delays contributed by individual architectural elements
are called internal timing parameters, which cannot be measured explicitly. All
internal parameters are shown in italic type.
defines the internal timing
microparameters for the MAX II device family.
Table 16–2.
Internal Timing Microparameters (Part 1 of 2)
Parameter
t
LUT
t
COMB
t
CLR
t
PRE
t
SU
t
H
t
CO
t
C
t
FASTIO
t
IN
t
GLOB
Description
LE combinational LUT delay for data-in to data-out.
Combinational path delay. The delay from the time when a combinational logic signal from the LUT
bypasses the LE register to the time it becomes available at the LE output.
LE register clear delay. The delay from the assertion of the register’s asynchronous clear input to the time
the register output stabilizes at logical low.
LE register preset delay. The delay from the assertion of the register’s asynchronous preset input to the
time the register output stabilizes at logical high.
LE register setup time before clock. The time required for a signal to be stable at the register's data and
enable inputs before the register clock rising edge to ensure that the register correctly stores the input data.
LE register hold time after clock. The time required for a signal to be stable at the register's data and enable
inputs after the register clock's rising edge to ensure that the register correctly stores the input data.
LE register clock-to-output delay. The delay from the rising edge of the register's clock to the time the data
appears at the register output.
Register control delay. The time required for a signal to be routed to the clock, preset, or clear input of an
LE register.
Combinational output delay.
t
FASTIO
is the time required for a combinational signal from the LE adjacent to the
I/O block using the fast I/O connection.
I/O input pad and buffer delay. The
t
IN
applies to I/O pins used as inputs.
t
GLOB
applies to
GCLK
pins when used for global signals.
t
GLOB
is the delay required for a global signal to be
routed from the
GCLK
pins to the LAB column clocks through the global clock network.
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