17. Understanding and Evaluating Power
in MAX II Devices
MII51018-2.1
Introduction
Power consumption has become an important factor for CPLD applications with the
increased use of CPLDs in low power designs. Overall low standby (static) and
dynamic power is becoming increasingly important to reduce system power, and can
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be achieved with MAX II devices which have low stand-by and dynamic power.
This chapter contains the following sections:
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“Power in MAX II Devices” on page 17–1
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“MAX II Power Estimation Using the PowerPlay Early Power Estimator” on
page 17–3
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“PowerPlay Early Power Estimator Inputs” on page 17–3
“Power Estimation Summary” on page 17–13
“Power Saving Techniques” on page 17–15
Power in MAX II Devices
Different from previous CPLD architectures, MAX II logic does not use sense
amplifiers that require bias currents to amplify signal voltages within the device.
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Additionally, with the Quartus II software, efficient implementation of most
interconnects with local routing in MAX II devices significantly lowers the dynamic
power. Figure 17–1 shows the typical power consumption versus frequency for MAX
II devices. The power consumption (mWatts) provided is based on typical conditions
using a pattern that fills a device with a 16-bit, loadable, enabled, up/down counter
with no output load.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
