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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC and Switching Characteristics  
Table 5–22. Routing Delay Internal Timing Microparameters  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Routing  
Unit  
Min  
Max  
429  
326  
330  
Min  
Max  
556  
423  
429  
Min  
Max  
Min  
Max  
(1)  
Min  
Max  
(1)  
tC4  
tR4  
tLOCAL  
687  
521  
529  
ps  
ps  
ps  
(1)  
(1)  
(1)  
(1)  
Note to Table 5–22:  
(1) The numbers will only be available in a later revision.  
External Timing Parameters  
External timing parameters are specified by device density and speed  
grade. All external I/O timing parameters shown are for the 3.3-V LVTTL  
I/O standard with the maximum drive strength and fast slew rate. For  
external I/O timing using standards other than LVTTL or for different  
drive strengths, use the I/O standard input and output delay adders in  
Tables 5–27 through 5–31.  
f
For more information about each external timing parameters symbol,  
refer to the Understanding Timing in MAX II Devices chapter in the  
MAX II Device Handbook.  
Altera Corporation  
July 2008  
5–21  
MAX II Device Handbook, Volume 1  
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