EPM1270GT144I4N 参数 Datasheet PDF下载

型号：	EPM1270GT144I4N
PDF下载：	下载PDF文件查看货源
内容描述：	[Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用：	LTE输入元件可编程逻辑
文件页数/大小：	108 页 / 1342 K
品牌：	ALTERA [ ALTERA CORPORATION ]

Timing Model and Specifications

Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)

–3 Speed

Grade

–4 Speed

Grade

–5 Speed

Grade

–6 Speed

Grade

–7 Speed

Grade

Symbol

Parameter

Unit

Min Max Min Max Min Max Min Max Min Max

t_PB

Maximum delay

between program

rising edge to

UFM busy signal

rising edge

—

960

—

960

—

960

—

960

—

960

t_BP

Minimum delay

allowedfromUFM

busy signal going

low to program

signal going low

—

t_PPMX

Maximum length

of busy pulse

during a program

—

100

—

100

—

100

—

100

—

100

—

µs

t_AE

Minimum erase

signal to address

clock hold time

t_EB

Maximum delay

between the

—

960

—

960

—

960

—

960

—

960

erase rising edge

to the UFM busy

signal rising edge

t_BE

Minimum delay

allowed from the

UFM busy signal

going low to erase

signal going low

—

t_EPMX

Maximum length

of busy pulse

during an erase

—

500

—

500

—

500

—

500

—

500

t_DCO

Delay from data

data register

output

t_OE

Delay from data

data register

output

180

—

180

—

180

—

180

—

180

—

5–18Core Version a.b.c variable

MAX II Device Handbook, Volume 1

Altera Corporation

July 2008

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EPM1270GT144I4N 参数 Datasheet PDF下载

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