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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC and Switching Characteristics  
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 3)  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Symbol  
Parameter  
Unit  
Min Max Min Max Min Max Min Max Min Max  
tACLK  
tASU  
Address register  
clock period  
100  
100  
100  
100  
100  
ns  
ns  
Address register  
shift signal setup  
to address  
20  
20  
20  
20  
20  
register clock  
tAH  
Address register  
shift signal hold to  
address register  
clock  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
ns  
ns  
ns  
tADS  
Address register  
data in setup to  
address register  
clock  
tADH  
Address register  
data in hold from  
address register  
clock  
tDCLK  
tDSS  
Data register  
clock period  
100  
60  
100  
60  
100  
60  
100  
60  
100  
60  
ns  
ns  
Data register shift  
signal setup to  
data register clock  
tDSH  
tDDS  
tDDH  
tDP  
Data register shift  
signal hold from  
data register clock  
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
20  
20  
20  
0
ns  
ns  
ns  
ns  
Data register data  
in setup to data  
register clock  
Data register data  
in hold from data  
register clock  
Program signal to  
data clock hold  
time  
Altera Corporation  
July 2008  
5–17  
MAX II Device Handbook, Volume 1  
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