Serial Configuration Device Memory Access
Figure 4–5. Write Enable Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
DCLK
Operation Code
ASDI
DATA
High Impedance
Write Disable Operation
The write disable operation code is b'0000 0100, with the MSB listed
first. The write disable operation resets the write enable latch bit, which
is bit 1 in the status register. To prevent the memory from being written
unintentionally, the write enable latch bit is automatically reset when
implementing the write disable operation as well as under the following
conditions:
■
■
■
■
■
Power up
Write bytes operation completion
Write status operation completion
Erase bulk operation completion
Erase sector operation completion
Figure 4–6 shows the timing diagram for the write disable operation.
Figure 4–6. Write Disable Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
DCLK
Operation Code
ASDI
DATA
High Impedance
4–12
Configuration Handbook, Volume 2
Core Version a.b.c variable
Altera Corporation
July 2004
ALTERA [ ALTERA CORPORATION ]
