Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
All attempts to access the memory contents while a write or erase cycle is
in progress will not be granted, and the write or erase cycle will continue
unaffected.
Table 4–8. Operation Codes for Serial Configuration Devices
DCLK fMAX
(MHz)
Operation
Operation Code (1) Address Bytes
Dummy Bytes
Data Bytes
Write enable
Write disable
Read status
Read bytes
Read silicon ID
Write status
Write bytes
Erase bulk
0
0
0
3
0
0
3
0
3
0
0
0
0
3
0
0
0
0
0
25
25
25
20
25
25
25
25
25
0000 0110
0000 0100
0000 0101
0000 0011
1010 1011
0000 0001
0000 0010
1100 0111
1101 1000
0
1 to infinite (2)
1 to infinite (2)
1 to infinite (2)
1
1 to 256 (3)
0
0
Erase sector
Notes to Table 4–8:
(1) The MSB is listed first and the least significant bit (LSB) is listed last.
(2) The status register, data or silicon ID are read out at least once on the DATApin and will continuously be read out
until nCSis driven high
(3) Write bytes operation requires at least one data byte on the DATApin. If more than 256 bytes are sent to the device,
only the last 256 bytes are written to the memory.
Write Enable Operation
The write enable operation code is b'0000 0110, and the most
significant bit is listed first. The write enable operation sets the write
enable latch bit, which is bit 1 in the status register. Always set the write
enable latch bit before write bytes, write status, erase bulk, and erase
sector operations. Figure 4–5 shows the timing diagram for the write
enable operation. Figures 4–7 and 4–8 show the status register bit
definitions.
Altera Corporation
July 2004
Core Version a.b.c variable
4–11
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
