Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Read Status Operation
The read status operation code is b'0000 0101, with the MSB listed first.
You can use the read status operation to read the status register.
Figures 4–7 and 4–8 show the status bits in the status register of both
serial configuration devices.
Figure 4–7. EPCS4 Status Register Status Bits
Bit 7
Bit 0
WIP
BP2
BP1
BP0
WEL
Block Protect Bits [2..0]
Write In
Progress Bit
Write Enable
Latch Bit
Figure 4–8. EPCS1 Status Register Status Bits
Bit 7
Bit 0
WIP
BP1
BP0
WEL
Block Protect
Bits [1..0]
Write In
Progress Bit
Write Enable
Latch Bit
Setting the write in progress bit to 1 indicates that the serial configuration
device is busy with a write or erase cycle. Resetting the write in progress
bit to 0 means no write or erase cycle is in progress.
Resetting the write enable latch bit to 0indicates that no write or erase
cycle will be accepted. Set the write enable latch bit to 1before every write
bytes, write status, erase bulk, and erase sector operation.
The non-volatile block protect bits determine the area of the memory
protected from being written or erased unintentionally. Tables 4–9 and
4–10 show the protected area in both serial configuration devices with
reference to the block protect bits. The erase bulk operation is only
Altera Corporation
July 2004
Core Version a.b.c variable
4–13
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
