Serial Configuration Device Memory Access
Table 4–7. Address Range for Sectors in EPCS1 Devices
Address Range (Byte Addresses in HEX)
Sector
Start
End
3
2
1
0
H'18000
H'10000
H'08000
H'00000
H'1FFFF
H'17FFF
H'0FFFF
H'07FFF
Operation Codes
This section describes the operations that can be used to access the
memory in serial configuration devices. The DATA, DCLK, ASDI, and nCS
signals access to the memory in serial configuration devices. All serial
configuration device operation codes, addresses and data are shifted in
and out of the device serially, with the most significant bit (MSB) first.
The device samples the active serial data input on the first rising edge of
the DCLKafter the active low chip select (nCS) input signal is driven low.
Shift the operation code (MSB first) serially into the serial configuration
device through the active serial data input pin. Each operation code bit is
latched into the serial configuration device on the rising edge of the DCLK.
Different operations require a different sequence of inputs. While
executing an operation, you must shift in the desired operation code,
followed by the address bytes, data bytes, both, or neither. The device
must drive nCShigh after the last bit of the operation sequence is shifted
in. Table 4–8 shows the operation sequence for every operation
supported by the serial configuration devices.
For the read byte, read status, and read silicon ID operations, the shifted-
in operation sequence is followed by data shifted out on the DATApin.
You can drive the nCSpin high after any bit of the data-out sequence is
shifted out.
For the write byte, erase bulk, erase sector, write enable, write disable,
and write status operations, drive the nCSpin high exactly at a byte
boundary (drive the nCSpin high a multiple of eight clock pulses after the
nCSpin was driven low). Otherwise, the operation is rejected and will not
be executed.
4–10
Core Version a.b.c variable
Altera Corporation
July 2004
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
