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EPCS4SI8N 参数 Datasheet PDF下载

EPCS4SI8N图片预览
型号: EPCS4SI8N
PDF下载: 下载PDF文件 查看货源
内容描述: 串行配置器件 [Serial Configuration Devices]
分类和应用: 存储内存集成电路光电二极管过程控制系统PCSLTE可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 32 页 / 241 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet  
Figure 4–9. Read Status Operation Timing Diagram  
nCS  
DCLK  
ASDI  
DATA  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Operation Code  
Status Register Out  
Status Register Out  
High Impedance  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB  
MSB  
Write Status Operation  
The write status operation code is b'0000 0001, with the MSB listed  
first. Use the write status operation to set the status register block  
protection bits. The write status operation has no effect on the other bits.  
Therefore, designers can implement this operation to protect certain  
memory sectors, as defined in Tables 4–9 and 4–10. After setting the block  
protect bits, the protected memory sectors are treated as read-only  
memory. Designers must execute the write enable operation before the  
write status operation so the device sets the status register’s write enable  
latch bit to 1.  
The write status operation is implemented by driving nCSlow, followed  
by shifting in the write status operation code and one data byte for the  
status register on the ASDIpin. Figure 4–10 shows the timing diagram for  
the write status operation. nCSmust be driven high after the eighth bit of  
the data byte has been latched in, otherwise, the write status operation is  
not executed.  
Immediately after nCSis driven high, the device initiates the self-timed  
write status cycle. The self-timed write status cycle usually takes 5 ms for  
both serial configuration devices and is guaranteed to be less than 15 ms  
(see tWS in Table 4–12). Designers must account for this delay to ensure  
that the status register is written with desired block protect bits.  
Alternatively, you can check the write in progress bit in the status register  
by executing the read status operation while the self-timed write status  
cycle is in progress. The write in progress bit is 1 during the self-timed  
write status cycle, and is 0 when it is complete.  
Altera Corporation  
July 2004  
Core Version a.b.c variable  
4–15  
Configuration Handbook, Volume 2