Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–3. FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party
Programmer)
V
(1)
V
(1)
V
CC
(1)
CC
CC
10 kΩ
10 kΩ
10 kΩ
Stratix II or
Cyclone Series FPGA
CONF_DONE
nSTATUS
nCONFIG
nCEO
N.C.
Serial
Configuration
Device (2)
n
nCE
MSEL[n]
(3)
DATA
DCLK
nCS
DATA0
DCLK
nCSO
ASDO
ASDI
Notes to Figures 4–2 and 4–3:
(1) VCC = 3.3-V.
(2) Serial configuration devices cannot be cascaded.
(3) Connect the FPGA MSEL[]input pins to select the AS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
The FPGA acts as the configuration master in the configuration flow and
provides the clock to the serial configuration device. The FPGA enables
the serial configuration device by pulling the nCSsignal low via the nCSO
signal (See Figures 4–2 and 4–3). Subsequently, the FPGA sends the
instructions and addresses to the serial configuration device via the ASDO
signal. The serial configuration device responds to the instructions by
sending the configuration data to the FPGA’s DATA0pin on the falling
edge of DCLK. The data is latched into the FPGA on the DCLKsignal’s
rising edge.
The FPGA controls the nSTATUSand CONF_DONEpins during
configuration in AS mode. If the CONF_DONEsignal does not go high at
the end of configuration or if the signal goes high too early, the FPGA will
pulse its nSTATUSpin low to start reconfiguration. Upon successful
configuration, the FPGA releases the CONF_DONEpin, allowing the
external 10-kΩresistor to pull this signal high. Initialization begins after
the CONF_DONEgoes high. After initialization, the FPGA enters user
mode.
f
For more information on configuring Stratix II FPGAs in AS mode or
other configuration modes, see Configuring Stratix II Devices in the
Configuration Handbook.
Altera Corporation
July 2004
Core Version a.b.c variable
4–7
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
