1–22
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (Note 1) (Part 2
of 2)
C6
C7, I7
C8, A7
Symbol
TCCS
Modes
Unit
Min
Max
Min
Max
Min
Max
—
—
—
—
200
—
—
—
200
—
—
—
200
ps
ps
Output jitter
(peak to peak)
—
—
500
1
500
1
550
1
tLOCK (2)
ms
Notes to Table 1–30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications (Note 1)
C6
C7, I7
Min
C8, A7
Symbol
Modes
Unit
Min
10
10
10
10
10
10
100
80
70
40
20
10
—
Max
437.5
437.5
437.5
437.5
437.5
437.5
875
Max
370
370
370
370
370
402.5
740
740
740
740
740
402.5
400
Min
10
10
10
10
10
10
100
80
70
40
20
10
—
Max
320
320
320
320
320
402.5
640
640
640
640
640
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
10
10
10
10
10
10
100
80
70
40
20
10
—
MHz
MHz
MHz
f
HSCLK (input clock
frequency)
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
875
875
HSIODR
SW
875
875
437.5
400
402.5 Mbps
400
550
1
ps
Input jitter
tolerance
—
—
—
—
500
1
—
—
500
1
—
—
ps
tLOCK (2)
ms
Notes to Table 1–31:
(1) LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
