1–18
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.
Table 1–25. Cyclone III Devices JTAG Timing Parameters
Symbol Parameter
tJCP
(Note 1)
Min
40
20
20
1
Max
—
—
—
—
—
—
15
15
15
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock period
TCK clock high time
TCK clock low time
tJCH
tJCL
tJPSU_TDI
tJPSU_TMS
tJPH
JTAG port setup time for TDI (2)
JTAG port setup time for TMS (2)
JTAG port hold time
3
10
—
—
—
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time (2)
Capture register hold time
10
—
—
—
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Notes to Table 1–25:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
High-Speed I/O Specifications
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
(Note 1), (2) (Part 1 of 2)
C7, I7 C8, A7
Min Typ Max Min Typ Max Min Typ Max
C6
Symbol
Modes
Unit
×10
×8
×7
×4
×2
×1
10
10
10
10
10
10
—
—
—
—
—
—
180
180
180
180
180
360
10
10
10
10
10
10
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
10
10
10
10
10
10
—
—
—
—
—
—
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
fHSCLK
(input clock
frequency)
311
MHz
Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
