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EP3C25F256C8NES 参数 Datasheet PDF下载

EP3C25F256C8NES图片预览
型号: EP3C25F256C8NES
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 24624 CLBs, 472.5MHz, PBGA256, 17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 367 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–20  
Chapter 1: Cyclone III Device Data Sheet  
Switching Characteristics  
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (Note 1) (Part 2 of 2)  
C6  
C7, I7  
Typ  
C8, A7  
Typ  
Symbol  
Modes  
Unit  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
20 – 80%,  
CLOAD = 5 pF  
20 – 80%,  
CLOAD = 5 pF  
tRISE  
500  
500  
500  
ps  
tFALL  
500  
1
500  
1
500  
1
ps  
tLOCK (2)  
ms  
Notes to Table 1–27:  
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.  
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (Note 1), (2)  
C6  
C7, I7  
Typ Max  
C8, A7  
Symbol  
Modes  
Unit  
Min  
10  
10  
10  
10  
10  
10  
100  
80  
70  
40  
20  
10  
45  
Typ Max  
Min  
10  
10  
10  
10  
10  
10  
100  
80  
70  
40  
20  
10  
45  
Min  
10  
10  
10  
10  
10  
10  
100  
80  
70  
40  
20  
10  
45  
Typ  
Max  
155.5  
155.5  
155.5  
155.5  
155.5  
311  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
200  
200  
200  
200  
200  
400  
400  
400  
400  
400  
400  
400  
55  
155.5  
155.5  
155.5  
155.5  
155.5  
311  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
fHSCLK (input  
clock  
frequency)  
311  
311  
311  
311  
Device  
operation in  
Mbps  
311  
311  
311  
311  
311  
311  
311  
311  
tDUTY  
55  
55  
TCCS  
200  
200  
200  
ps  
Output jitter  
(peak to  
peak)  
500  
500  
550  
ps  
ps  
20 – 80%,  
CLOAD = 5 pF  
20 – 80%,  
CLOAD = 5 pF  
tRISE  
500  
500  
500  
tFALL  
500  
1
500  
1
500  
1
ps  
tLOCK (3)  
ms  
Notes to Table 1–28:  
(1) Applicable for true and emulated mini-LVDS transmitter.  
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported  
at the output pin of all I/O banks.  
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Cyclone III Device Handbook, Volume 2  
© January 2010 Altera Corporation  
 
 
 
 
 
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