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EP3C25F256C8NES 参数 Datasheet PDF下载

EP3C25F256C8NES图片预览
型号: EP3C25F256C8NES
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 24624 CLBs, 472.5MHz, PBGA256, 17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 367 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–26  
Chapter 1: Cyclone III Device Data Sheet  
Switching Characteristics  
IOE Programmable Delay  
Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.  
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (Note 1), (2)  
Max Offset  
Slow Corner  
C8  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Unit  
Settings  
C6  
C7  
I7  
A7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.211 1.314 2.175  
2.32  
2.386 2.366  
2.49  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
1.203 1.307  
2.19  
2.387  
2.54  
2.43  
2.545  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
0.479 0.504 0.915 1.011 1.107 1.018 1.048  
0.664 0.694 1.199 1.378 1.532 1.392 1.441  
Input delay from  
Pad to global  
dual-purpose clock pin clock  
to fan-out destinations network  
12  
0
ns  
Notes to Table 1–37:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.  
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins  
(Note 1), (2)  
Max Offset  
Slow Corner  
C8  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Unit  
Settings  
C6  
C7  
I7  
A7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.209 1.314 2.174 2.335 2.406 2.381 2.505  
1.207 1.312 2.202 2.402 2.558 2.447 2.557  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
0.51  
0.537 0.962 1.072 1.167 1.074 1.101  
Input delay from  
dual-purpose clock pin  
to fan-out destinations  
Pad to global  
clock network  
12  
0
0.669 0.698 1.207 1.388 1.542 1.403  
1.45  
ns  
Notes to Table 1–38:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software  
Cyclone III Device Handbook, Volume 2  
© January 2010 Altera Corporation  
 
 
 
 
 
 
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