Chapter 1: Cyclone III Device Data Sheet
1–25
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (Note 1) (Part 2 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory
I/O Standard
Standard
Lead
1092
1250
Lag
515
662
Lead
Lag
515
662
Lead
1192
1350
Lag
615
762
1.8 V HSTL Class I
1.8 V HSTL Class II
1092
1250
QDRII SRAM
Notes to Table 1–33:
(1) Column I/Obanks refer to top and bottom I/Os. Row I/Obanks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (Note 1), (2)
Parameter
Clock period jitter
Symbol
tJIT(per)
Min
-125
-200
-150
Max
125
200
150
Unit
ps
Cycle-to-cycle period jitter
Duty cycle jitter
tJIT(cc)
ps
tJIT(duty)
ps
Notes to Table 1–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specifications
Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
(Note 1), (2)
C6
C7, I7
Max
55
C8, A7
Symbol
Unit
Min
Max
Min
Min
Max
55
Output Duty Cycle
45
55
45
45
%
Notes to Table 1–35:
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
OCT Calibration Timing Specification
Table 1–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
Power-Up (Note 1)
Maximum
Symbol
Description
Unit
Duration of series OCT with
calibration at device power-up
tOCTCAL
20
µs
Notes to Table 1–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
© January 2010 Altera Corporation
Cyclone III Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
