IEEE Std. 1149.1 BST Operation Control
When the TAP controller is in the TEST_LOGIC/RESETstate, the BST
circuitry is disabled, the device is in normal operation, and the instruction
register is initialized with IDCODEas the initial instruction. At device
power-up, the TAP controller starts in this TEST_LOGIC/RESETstate. In
addition, forcing the TAP controller to the TEST_LOGIC/RESETstate is
done by holding TMShigh for five TCKclock cycles. Once in the
TEST_LOGIC/RESETstate, the TAP controller remains in this state as
long as TMSis held high (while TCKis clocked). Figure 14–6 shows the
timing requirements for the IEEE Std. 1149.1 signals.
Figure 14–6. IEEE Std. 1149.1 Timing Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
tJPZX
tJPXZ
tJPCO
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
To start IEEE Std. 1149.1 operation, select an instruction mode by
advancing the TAP controller to the shift instruction register (SHIFT_IR)
state and shift in the appropriate instruction code on the TDIpin. The
waveform diagram in Figure 14–7 represents the entry of the instruction
code into the instruction register. It shows the values of TCK, TMS, TDI,
TDO, and the states of the TAP controller. From the RESETstate, TMSis
clocked with the pattern 01100to advance the TAP controller to
SHIFT_IR.
14–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
