IEEE Std. 1149.1 BST Operation Control
Figure 14–10 shows the capture, shift, and update phases of the EXTEST
mode.
Figure 14–10. IEEE Std. 1149.1 BST EXTEST Mode
Capture Phase
SDO
In the capture phase, the
signals at the pin, OEJ and
OUTJ, are loaded into the
capture registers. The CLOCK
signals are supplied by the
0
1
0
1
INJ
D
Q
D
Q
TAP controller’s CLOCKDR
output. Previously retained
data in the update registers
drive the PIN_IN, INJ, and
allows the I/O pin to tri-state
OEJ
0
1
0
1
D
D
Q
Q
D
D
Q
Q
or drive a signal out.
OUTJ
0
1
0
1
A “1” in the OEJ update
register tri-states the output
buffer.
Capture
Update
Registers
Registers
SHIFT
CLOCK
UPDATE
MODE
SDI
Shift & Update Phases
SDO
0
0
In the shift phase, the
INJ
1
D
Q
D
Q
1
previously captured signals at
the pin, OEJ and OUTJ, are
shifted out of the boundary-
scan register via the TDO pin
OEJ
0
1
using CLOCK. As data is
shifted out, the patterns for
the next test can be shifted in
via the TDI pin.
0
1
D
D
Q
Q
D
D
Q
Q
OUTJ
0
1
In the update phase, data is
transferred from the capture
registers to the update
0
1
registers using the UPDATE
clock. The update registers
then drive the PIN_IN, INJ,
and allow the I/O pin to tri-
state or drive a signal out.
Capture
Registers
Update
Registers
UPDATE
MODE
SDI
SHIFT
CLOCK
14–12
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
