IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
to external device data via the PIN_INsignal, while the update registers
connect to external data through the PIN_OUTand PIN_OEsignals. The
global control signals for the IEEE Std. 1149.1 BST registers (for example,
shift, clock, and update) are generated internally by the TAP controller.
The MODEsignal is generated by a decode of the instruction register. The
data signal path for the boundary-scan register runs from the serial data
in (SDI) signal to the serial data out (SDO) signal. The scan register begins
at the TDIpin and ends at the TDOpin of the device.
Figure 14–4 shows the Cyclone II device’s user I/O boundary-scan cell.
Figure 14–4. Cyclone II Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry
Capture
Registers
Update
Registers
SDO
INJ
PIN_IN
0
1
0
1
D
Q
D
Q
INPUT
INPUT
OEJ
From or
To Device
I/O Cell
Circuitry
and/or
0
1
0
1
PIN_OE
D
Q
D
Q
0
1
OE
OE
Logic
Array
V
CC
OUTJ
0
1
PIN_OUT
Pin
0
1
D
Q
D
Q
Output
Buffer
OUTPUT
OUTPUT
SDI
Global
Signals
SHIFT
CLOCK
UPDATE HIGHZ MODE
Altera Corporation
February 2007
14–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
