IEEE Std. 1149.1 BST Operation Control
Table 14–2 describes the capture and update register capabilities of all
types of boundary-scan cells within Cyclone II devices.
Table 14–2. Cyclone II Device Boundary Scan Cell Descriptions Note (1)
Captures
OE
Drives
Output
Capture
Register
Input
Output
Update
OE
Update
Input
Update
Pin Type
Comments
Capture Capture
Register Register Register Register Register
User I/O pins
OUTJ
OEJ
PIN_IN PIN_OUT PIN_OE
INJ
Dedicated clock
input
0
1
N.C. (2)
N.C. (2)
N.C. (2)
PIN_IN
PIN_INdrivesto
clock network or
logic array
Dedicated input
(3)
0
0
1
N.C. (2)
N.C. (2)
N.C. (2)
N.C. (2)
N.C. (2)
N.C. (2)
PIN_IN
PIN_IN
PIN_INdrives to
control logic
Dedicated
bidirectional
(open drain) (4)
OEJ
PIN_INdrives to
configuration
control
Dedicated
N.C. (2)
N.C. (2)
N.C. (2)
OUTJ
OEJ
PIN_IN
OUTJdrives to
bidirectional (5)
output buffer
Notes to Table 14–2:
(1) TDI, TDO, TMS, TCK, all VCC and GND pin types do not have BSCs.
(2) N.C.: no connect.
(3) This includes nCONFIG, MSEL0, MSEL1, DATA0, and nCEpins and DCLK(when not used in Active Serial mode).
(4) This includes CONF_DONEand nSTATUSpins.
(5) This includes DCLK(when not used in Active Serial mode).
Cyclone II devices implement the following IEEE Std. 1149.1 BST
instructions: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE, USERCODE,
CLAMP,and HIGHZ. The BST instruction length is 10 bits. These
instructions are described later in this chapter.
IEEE Std. 1149.1
BST Operation
Control
f
For summaries of the BST instructions and their instruction codes, see
the Configuration & Testing chapter in Volume 1 of the Cyclone II Device
Handbook.
The IEEE Std. 1149.1 test access port (TAP) controller, a 16-state state
machine clocked on the rising edge of TCK, uses the TMSpin to control
IEEE Std. 1149.1 operation in the device. Figure 14–5 shows the TAP
controller state machine.
14–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
