IEEE Std. 1149.1 BST Operation Control
Figure 14–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
SDO
Capture Phase
0
1
0
INJ
In the capture phase, the
signals at the pin, OEJ and
D
Q
D
Q
1
OUTJ, are loaded into the
capture registers. The CLOCK
signals are supplied by the
TAP controller’s CLOCKDR
output. The data retained in
these registers consists of
signals from normal device
operation.
OEJ
0
1
0
D
Q
Q
D
D
Q
Q
1
OUTJ
0
1
0
1
D
Capture
Update
Registers
Registers
Shift & Update Phases
SDI
SHIFT
CLOCK
UPDATE
MODE
In the shift phase, the
previously captured signals at
the pin, OEJ and OUTJ, are
shifted out of the boundary-
scan register via the TDO pin
using CLOCK. As data is
shifted out, the patterns for
the next test can be shifted in
via the TDI pin.
SDO
0
1
0
1
INJ
D
Q
D
Q
OEJ
In the update phase, data is
transferred from the capture
to the UPDATE registers using
the UPDATE clock. The data
stored in the UPDATE
registers can be used for the
EXTEST instruction.
0
1
0
1
D
D
Q
Q
D
D
Q
Q
OUTJ
0
1
0
1
Capture
Update
Registers
Registers
MODE
SDI
SHIFT
UPDATE
CLOCK
14–10
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
