DC & Switching Characteristics
Table 6–87. High-Speed I/O Specifications (Part 3 of 4)
Notes (1), (2)
-6 Speed Grade
-5 Speed Grade
-7 Speed Grade
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max
DPA Lock Time Standard Train Trans
ing ition
Patt Den-
ern sity
SPI-4,
CSIX
0000 10%
0000
256
256
256
(4)
0011
1111
1111
Rapid IO 0000 25%
1111
256
256
256
256
256
256
256
256
256
256
256
256
(4)
(4)
(4)
(4)
1001 50%
0000
Misc
1010 100
1010 %
0101
0101
TCCS
SW
All
200
200
300
ps
ps
ps
ps
ps
PCML (J = 4, 7, 8, 10)
PCML (J = 2)
750
900
750
900
800
1,200
1,700
550
PCML (J = 1)
1,500
500
1,500
500
LVDS and LVPECL
(J = 1)
LVDS, LVPECL,
HyperTransport
technology (J = 2
through 10)
440
440
500
ps
Input jitter
tolerance
(peak-to-peak)
All
250
250
250
ps
ps
Output jitter
All
160
160
200
(peak-to-peak)
Output tRISE
LVDS
80
110 120
80
110 120
80
110 120
ps
ps
HyperTransport
technology
110 170 200
110 170 200
120 170 200
LVPECL
PCML
90
80
130 150
110 135
90
80
130 150
110 135
100 135 150
ps
ps
80
110 135
Altera Corporation
June 2006
6–61
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
