High-Speed I/O Specification
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
fOUT
Output frequency for internal global or
regional clock
0.3
450
MHz
fOUT_EXT
tOUTDUTY
Output frequency for external clock (2) 0.3
500
55
MHz
%
Duty cycle for external clock output
45
(when set to 50%)
tJITTER
Period jitter for external clock output (5)
100 ps for >200 MHz outclk
20 mUI for <200 MHz outclk
ps or
mUI
tCONFIG5,6
tCONFIG11,12
Time required to reconfigure the scan
chains for PLLs 5 and 6
289/fSCANCLK
Time required to reconfigure the scan
chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (4)
22
MHz
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6) (10)
100
μs
tLOCK
Time required to lock from end of
10
400
μs
device configuration (10)
fVCO
PLL internal VCO operating range
300
800 (7)
MHz
ps
tLSKEW
Clock skew between two external clock
outputs driven by the same counter
50
75
tSKEW
Clock skew between two external clock
outputs driven by the different counters
with the same settings
ps
fSS
Spread spectrum modulation frequency 30
150
0.6
kHz
%
% spread
Percentage spread for spread
0.4 0.5
spectrum frequency (9)
tARESET
10
ns
Minimum pulse width on areset
signal
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 3)
Symbol
Parameter
Min Typ
Max
565
60
Unit
MHz
%
fIN
Input clock frequency
3 (1)
40
fINDUTY
Input clock duty cycle
fEINDUTY
External feedback clock input duty
cycle
40
60
%
tINJITTER
Input clock period jitter
200 (2)
200 (2)
ps
ps
tEINJITTER
External feedback clock period jitter
6–64
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
