DC & Switching Characteristics
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
tOUTDUTY
Duty cycle for external clock output
45
55
%
(when set to 50%)
tJITTER
Period jitter for external clock output (5)
100 ps for >200 MHz outclk
20 mUI for <200 MHz outclk
ps or
mUI
tCONFIG5,6
tCONFIG11,12
Time required to reconfigure the scan
chains for PLLs 5 and 6
289/fSCANCLK
Time required to reconfigure the scan
chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (4)
22
MHz
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays) (6)
100
μs
tLOCK
Time required to lock from end of
device configuration
10
400
μs
fVCO
PLL internal VCO operating range
300
50
800 (7)
MHz
ps
tLSKEW
Clock skew between two external clock
outputs driven by the same counter
tSKEW
Clock skew between two external clock
outputs driven by the different counters
with the same settings
75
ps
fSS
Spread spectrum modulation frequency 30
150
0.6
kHz
%
% spread
Percentage spread for spread
0.4 0.5
spectrum frequency (9)
tARESET
10
ns
Minimum pulse width on areset
signal
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades (Part 1 of 2)
Symbol
Parameter
Min Typ
3 (1)
40
Max
650
60
Unit
MHz
%
fIN
Input clock frequency
fINDUTY
Input clock duty cycle
fEINDUTY
External feedback clock input duty
cycle
40
60
%
tINJITTER
tEINJITTER
tFCOMP
Input clock period jitter
200 (2)
200 (2)
6
ps
ps
ns
External feedback clock period jitter
External feedback clock compensation
time (3)
Altera Corporation
June 2006
6–63
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
