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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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High-Speed I/O Specification  
Table 6–87. High-Speed I/O Specifications (Part 4 of 4)  
Notes (1), (2)  
-5 Speed Grade  
-6 Speed Grade  
-7 Speed Grade  
Symbol  
Conditions  
Unit  
Min Typ Max Min Typ Max Min Typ Max  
Output tFALL  
LVDS  
80  
110 120  
80  
110 120  
80  
110 120  
ps  
ps  
HyperTransport  
technology  
110 170 200  
110 170 200  
110 170 200  
LVPECL  
PCML  
90  
130 160  
90  
130 160  
100 135 160  
110 145 175  
ps  
ps  
%
105 140 175  
105 140 175  
tDUTY  
LVDS (J = 2 through  
47.5 50 52.5 47.5 50 52.5 47.5  
50 52.5  
10)  
LVDS (J =1) and  
LVPECL, PCML,  
HyperTransport  
technology  
45  
50  
55  
45  
50  
55  
45  
50  
55  
%
tLOCK  
All  
100  
100  
100  
μs  
Notes to Table 6–87:  
(1) When J = 4, 7, 8, and 10, the SERDES block is used.  
(2) When J = 2 or J = 1, the SERDES is bypassed.  
(3) Number of parallel CLKcycles.  
(4) Number of repetitions.  
PLL Timing  
Tables 6–88 through 6–90 describe the Stratix GX device enhanced PLL  
specifications.  
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)  
Symbol  
Parameter  
Min Typ  
3 (1)  
40  
Max  
684  
60  
Unit  
MHz  
%
fIN  
Input clock frequency  
fINDUTY  
Input clock duty cycle  
fEINDUTY  
External feedback clock input duty  
cycle  
40  
60  
%
tINJITTER  
tEINJITTER  
tFCOMP  
Input clock period jitter  
200 (2)  
200 (2)  
6
ps  
ps  
ns  
External feedback clock period jitter  
External feedback clock compensation  
time (3)  
fOUT  
Output frequency for internal global or  
regional clock  
0.3  
0.3  
500  
526  
MHz  
MHz  
fOUT_EXT  
Output frequency for external clock (2)  
6–62  
Altera Corporation  
June 2006  
Stratix GX Device Handbook, Volume 1  
 
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