High-Speed I/O Specification
Table 6–85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 2 of 2)
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
1.5 V
350
400
200
200
167
167
150
150
150
150
250
225
250
225
400
400
400
300
225
717
717
420
420
300
350
167
167
150
150
133
133
133
133
225
225
225
225
350
350
350
250
225
717
717
420
420
300
300
125
125
133
133
133
133
133
133
200
200
200
200
300
300
300
200
200
500
500
420
420
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL class I
HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
Table 6–86 provides high-speed timing specifications definitions.
High-Speed I/O
Specification
Table 6–86. High-Speed Timing Specifications & Definitions (Part 1 of 2)
High-Speed Timing Specification Definitions
tC
fHSCLK
tRISE
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
6–58
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
