DC & Switching Characteristics
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3)
Symbol
Parameter
Min Typ
Max
Unit
tFCOMP
External feedback clock compensation
6
ns
time (3)
fOUT
Output frequency for internal global or
regional clock
0.3
420
MHz
fOUT_EXT
tOUTDUTY
Output frequency for external clock (2)
0.3
45
434
55
MHz
%
Duty cycle for external clock output
(when set to 50%)
tJITTER
Period jitter for external clock output (5)
100 ps for >200 MHz outclk
20 mUI for <200 MHz outclk
ps or
mUI
tCONFIG5,6
tCONFIG11,12
Time required to reconfigure the scan
chains for PLLs 5 and 6
289/fSCANCLK
Time required to reconfigure the scan
chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
tDLOCK
scanclkfrequency (4)
22
MHz
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6) (10)
100
μs
tLOCK
fVCO
Time required to lock from end of
device configuration (10)
10
400
μs
PLL internal VCO operating range
300
600 (7)
MHz
Altera Corporation
June 2006
6–65
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
