DC & Switching Characteristics
Table 6–84. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 2 of 2)
I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
1.8 V
250
225
350
200
200
167
167
200
200
150
150
250
225
250
225
350
350
350
350
350
200
225
200
500
500
350
350
250
200
300
167
167
150
150
200
200
133
133
225
200
225
200
300
300
300
300
300
200
200
200
500
500
350
350
250
200
250
125
125
133
133
167
167
133
133
200
200
200
200
250
250
250
250
250
200
200
167
500
500
350
350
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
Differential SSTL-2
LVDS
LVPECL
PCML
HyperTransport technology
Table 6–85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 1 of 2)
I/O Standard
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
LVTTL
2.5 V
1.8 V
400
400
400
350
350
350
300
300
300
MHz
MHz
MHz
Altera Corporation
June 2006
6–57
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
