Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 6–36 through 6–42 describe the
Stratix GX device internal timing microparameters for LEs, IOEs,
TriMatrix™ memory structures, DSP blocks, and MultiTrack
interconnects.
Table 6–36. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinational LUT delay for data-in to data-out
Minimum clear pulse width
tSU
tH
tCO
tLUT
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Table 6–37. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
tH
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinational output
Column input pin to IOE combinational output
Row IOE data input to combinational output pin
Column IOE data input to combinational output pin
Minimum clear pulse width
tCO
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
6–26
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
ALTERA [ ALTERA CORPORATION ]
