Timing Model
Table 6–40. M4K Block Internal Timing Microparameter Descriptions
Symbol Parameter
tM4KRC
Synchronous read cycle time
tM4KWC
Synchronous write cycle time
tM4KWERESU
tM4KWEREH
tM4KBESU
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
tM4KBEH
tM4KDATAASU
tM4KDATAAH
tM4KADDRASU
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
tM4KADDRBSU
tM4KADDRBH
tM4KDATACO1
tM4KDATACO2
tM4KCLKHL
tM4KCLR
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Parameter
tMRAMRC
Synchronous read cycle time
tMRAMWC
Synchronous write cycle time
tMRAMWERESU
tMRAMWEREH
tMRAMBESU
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
tMRAMBEH
tMRAMDATAASU
tMRAMDATAAH
tMRAMADDRASU
tMRAMADDRAH
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
6–28
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
ALTERA [ ALTERA CORPORATION ]
