DC & Switching Characteristics
Table 6–38. DSP Block Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
tH
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input register to DSP block pipeline register in 9 × 9-bit mode
tCO
tINREG2PIPE9
tINREG2PIPE18
Input register to DSP block pipeline register in 18 × 18-bit
mode
tPIPE2OUTREG2ADD
tPIPE2OUTREG4ADD
DSP block pipeline register to output register delay in two-
multipliers adder mode
DSP Block Pipeline Register to output register delay in four-
multipliers adder mode
tPD9
Combinational input to output delay for 9 × 9-bit mode
Combinational input to output delay for 18 × 18-bit mode
Combinational input to output delay for 36 × 36-bit mode
Minimum clear pulse width
tPD18
tPD36
tCLR
tCLKHL
Minimum clock high or low time
Table 6–39. M512 Block Internal Timing Microparameter Descriptions
Symbol Parameter
tM512RC
Synchronous read cycle time
tM512WC
Synchronous write cycle time
tM512WERESU
tM512WEREH
tM512DATASU
tM512DATAH
Write or read enable setup time before clock
Write or read enable hold time after clock
Data setup time before clock
Data hold time after clock
tM512WADDRSU
tM512WADDRH
tM512RADDRSU
tM512RADDRH
tM512DATACO1
tM512DATACO2
tM512CLKHL
tM512CLR
Write address setup time before clock
Write address hold time after clock
Read address setup time before clock
Read address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Altera Corporation
June 2006
6–27
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
