DC & Switching Characteristics
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
Parameter
tMRAMDATABSU
tMRAMDATABH
tMRAMADDRBSU
tMRAMADDRBH
tMRAMDATACO1
tMRAMDATACO2
tMRAMCLKHL
B port setup time before clock
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
tMRAMCLR
Minimum clear pulse width
Table 6–42. Routing Delay Internal Timing Microparameter Descriptions
Symbol
Parameter
tR4
Delay for an R4 line with average loading; covers a distance
of four LAB columns
tR8
Delay for an R8 line with average loading; covers a distance
of eight LAB columns
tR24
tC4
Delay for an R24 line with average loading; covers a distance
of 24 LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
tC8
Delay for an C8 line with average loading; covers a distance
of eight LAB rows
tC16
Delay for an C16 line with average loading; covers a distance
of 16 LAB rows
tLOCAL
Local interconnect delay
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 1 of 2)
Symbol
tANALOGRESETPW
tDIGITALRESETPW
tTX_PLL_LOCK
Parameter
Pulse width to power down analog circuits.
Pulse width to reset digital circuits
The time it takes the tx_pllto lock to the
reference clock.
Altera Corporation
June 2006
6–29
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
