DC & Switching Characteristics
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus® II software displays an informational message during the
design compilation if the timing models are preliminary. Table 6–34
shows the status of the Stratix GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 6–34. Stratix GX Device Timing Model Status
Device
Preliminary
Final
EP1SGX10
—
—
—
v
v
v
EP1SGX25
EP1SGX40
Performance
Table 6–35 shows Stratix GX device performance for some common
designs. All performance values were obtained with Quartus II software
compilation of LPM, or MegaCore® functions for the FIR and FFT
designs.
Table 6–35. Stratix GX Device Performance (Part 1 of 3)
Notes (1), (2)
Resources Used
Performance
-6 -7
Speed Speed Speed Units
Grade Grade Grade
TriMatrix
LEs Memory
Blocks
-5
Applications
DSP
Blocks
LE
16-to-1 multiplexer (1)
32-to-1 multiplexer (3)
16-bit counter
22
46
16
64
0
0
0
0
0
0
0
0
407.83 324.56 288.68
318.26 255.29 242.89
422.11 422.11 390.01
321.85 290.52 261.23
MHz
MHz
MHz
MHz
64-bit counter
Altera Corporation
June 2006
6–23
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
