DC & Switching Characteristics
Table 6–35. Stratix GX Device Performance (Part 3 of 3)
Notes (1), (2)
Resources Used
Performance
TriMatrix
LEs Memory
Blocks
-5
-6
-7
Applications
DSP
Blocks
Speed Speed Speed Units
Grade Grade Grade
True dual-port
RAM 16K × 36 bit
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
269.83 237.69 206.82
275.86 244.55 212.76
275.86 244.55 212.76
275.86 244.55 212.76
287.85 253.29 220.36
287.85 253.29 220.36
287.85 253.29 220.36
MHz
MHz
MHz
MHz
MHz
MHz
MHz
TriMatrix
memory
M-RAM
block
Single port
RAM 32K × 18 bit
Simple dual-port
RAM 32K × 18 bit
True dual-port
RAM 32K × 18 bit
Single port
RAM 64K × 9 bit
Simple dual-port
RAM 64K × 9 bit
True dual-port
RAM 64K × 9 bit
DSP block 9 × 9-bit multiplier (3)
18 × 18-bit multiplier (4)
36 × 36-bit multiplier (4)
36 × 36-bit multiplier (5)
18-bit, 4-tap FIR filter
0
0
0
0
0
0
0
0
5
1
1
1
1
1
4
1
335.0 293.94 255.68
278.78 237.41 206.52
148.25 134.71 117.16
278.78 237.41 206.52
278.78 237.41 206.52
141.26 133.49 114.88
261.09 235.51 205.21
MHz
MHz
MHz
MHz
MHz
MHz
MHz
0
0
0
Larger
8-bit, 16-tap parallel FIR filter
8-bit, 1,024-point FFT function
58
870
Designs
Notes to Table 6–35:
(1) These design performance numbers were obtained using the Quartus II software.
(2) Numbers not listed will be included in a future version of the data sheet.
(3) This application uses registered inputs and outputs.
(4) This application uses registered multiplier input and output stages within the DSP block.
(5) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
Altera Corporation
June 2006
6–25
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
