Timing Model
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 2 of 2)
Symbol
Parameter
tRX_FREQLOCK
The time until the clock recovery unit (CRU)
switches to data mode from lock to reference
mode.
tRX_FREQLOCK2PHASELOCK The time until CRU phase locks to data after
switching from lock to data mode.
Figure 6–4 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 6–39 through 6–41.
Figure 6–4. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
tWERESU
wren
tWADDRH
tWADDRSU
an-1
an
a0
a1
a2
a3
a4
a5
wraddress
data-in
a6
tDATAH
din-1
din4
din5
din6
din
tDATASU
rdclock
tWEREH
tWERESU
rden
tRC
rdaddress
bn
b1
b2
b3
b0
tDATACO1
doutn-1
doutn
dout0
reg_data-out
doutn-2
tDATACO2
doutn
doutn-1
dout0
unreg_data-out
6–30
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
